Input offsets in comparators are common. Currently, it is difficult to have sub milli-volt (sub-mV) offsets in comparators made by complementary metal oxide silicon (CMOS) technology. In attempts to achieve such sub-mV offsets, complex circuitries are used, including, for example, correlated double sampling (CDS), chopping, etc. In a CDS technique, the comparator samples a reference voltage, then samples an input signal in every clock cycle. The comparator result is based on the difference between the reference voltage and the input signal. Sampling the reference voltage, however, is difficult. In a chopping technique, a fully-differential system is used. Both differential input signals and differential output signals are swapped at a certain rate. As a result, effects of an offset are cancelled. Further, fixed-pattern noise is added, which subsequently needs to be filtered out.
Like reference symbols in the various drawings indicate like elements.